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PM8621 Datasheet(PDF) 92 Page - PMC-Sierra, Inc |
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PM8621 Datasheet(HTML) 92 Page - PMC-Sierra, Inc |
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92 / 184 page  NSE-8G™ Standard Product Data Sheet Preliminary Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 91 Document ID: PMC-2010850, Issue 1 Register 048H: DCB C1 delay (RC1DLY) register. Bit Type Function Default Bit 31-6 R Unused X Bit 13-0 R/W RC1DLY[13:0] 0 RC1DLY This value, equaling the delay (in 77.76 MHz clock periods), between RC1FP and the arrival of the C1 characters in the R8TD. This delay will synchronize the C1 input to the R8TD blocks assuming all the C1 characters have arrived. As the delay on those links is dependent on the system design, backplane propagation delays, cable lengths etc. This value will have to be arrived at empirically. And will have an upper an lower limit for which the middle value should be selected. The Operations section for more detail and some recommended starting values. MF_SWAP Legal Range (clock cycles) 00 26 – 9716 01 26 – 16383 10 26 – 16383 11 26 – 16383 |
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