GL9714 datasheet(35/46 Pages) GENESYS

35 / 46 page

GL9714 PCI Express

TM PIPE x4 PHY

Page 35

CHAPTER 7

ELECTRICAL CHARACTERISTICS

7.1 DC Electrical Characteristics

Table 7.1 - DC Electrical Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

VDD25

PHY Interface Voltage

2.375

2.5

2.625

VDD18

Core Voltage

1.71

1.8

1.89

VDD12

Reference Voltage for PHY Interface

1.1875

1.25

1.3125

VDDTXA

VDDTXB

VDDTXC

VDDTXD

Voltage for Transmitters

1.71

1.8

1.89

VDDRXA

VDDRXB

VDDRXC

VDDRXD

Voltage for Receivers

1.71

1.8

1.89

VDDPLL Voltage for PLL

1.71

1.8

1.89

7.2 Transmit and Receive Latency Time

Table 7.2 - Transmit and Receive Latency Time

Symbol

Parameter

Min

Typ

Max

Unit

TTX-LAT

Transmit Latency, time for data moving from

MAC interface (PCLK rising edge) to TX serial

lines (the first bit of 10-bit symbol)

TRX-LAT

Receive Latency, time for data moving from RX

serial lines (the first bit of 10-bit symbol) to

MAC interface (PCLK rising edge)

7.3 Transition Time of Power State

Table 7.3 – Transition Time of Power State

Symbol

Parameter

Min

Typ

Max

Unit

TP0S-P0

Time for PHY to return to P0, after having been

in P0s. Time is measured when PD[1:0] are set to

P0 until the PHY asserts PHYSTS

TP1-P0

Time for PHY to return to P0, after having been

in P1. Time is measured when PD[1:0] are set to

P0 until the PHY asserts PHYSTS

TP2-P1

Time for PHY to return to P0, after having been

in P2. Time is measured when PD[1:0] are set to

P0 until the PHY asserts PHYSTS

µs

TP0-P0S

Time for PHY to return to P0s, after having been

in P0. Time is measured when PD[1:0] are set to

P0 until the PHY asserts PHYSTS

TP0-P1

Time for PHY to return to P1, after having been

GL9714 Datasheet(PDF) 35 Page - GENESYS LOGIC

GL9714 Datasheet(HTML) 35 Page - GENESYS LOGIC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL