GL9714 datasheet(8/46 Pages) GENESYS

8 / 46 page

GL9714 PCI Express

TM PIPE x4 PHY

Page 8

CHAPTER 1

GENERAL DESCRIPTION

The GL9714 is a 4-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base

Specification rev. 1.0a and Intel’s PHY Interface for the PCI Express Architecture rev. 1.0. It integrates a quad

SerDes and the Physical Coding Sublayer (PCS) which performs 8b/10b encoding and decoding, elastic buffer

and receiver detection, data serialization and deserialization for each lane. The quad SerDes in the GL9714

supports an effective serial interface speed (2.5 Gb/s) of data bandwidth for each lane, intended for use in

ultrahigh-speed bi-directional data transmission system. The GL9714 can also be externally configured for

various combinations of lane number and parallel bus width which is flexible and suitable for x1, x2 or x4 lane

implementation. It also supports four operational states for power management to minimize power consumption.

For production and self-test purposes, the GL9714 provides BIST and an internal loopback capability.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband

data transmission over an on-chip termination resister of 50 Ohm +/- 10%.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the

number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered

to the receiver over a serial channel. It is then reconstructed into its original parallel format. The maximum data

transfer rate in each direction is 1 Giga byte per second with the 4-lane configuration. It also offers various

power saving modes to significantly reduce power consumption as well as scalability for a higher data rate in the

future.

GL9714 Datasheet(PDF) 8 Page - GENESYS LOGIC