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GL9714 Datasheet(PDF) 44 Page - GENESYS LOGIC

Part # GL9714
Description  PCI ExpressTM PIPE x4 PHY
PDF  46 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL9714 Datasheet(HTML) 44 Page - GENESYS LOGIC

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GL9714 PCI Express
TM PIPE x4 PHY
©2004-2007 Genesys Logic Inc. - All rights reserved.
Page 44
Table 8.5 – Input Setup, Hold Time and Output Timing for 10-bit DDR Mode
Symbol
Parameter
Min
Typ
Max
Unit
TCYCLE
PCLK cycle time
7.98
8
8.02
ns
Duty-H
Duty cycle for PCLK high
48
-
50
%
TIS
Input setup time
-
-
1.4
ns
TIH
Input hold time
0.5
-
-
ns
TCO
Clock to output delay
-
4.1
4.3
ns
TOH
Output hold time
3.5
3.7
-
ns
Note:
This table is based on design target, correlation data will be posted later.
8.2 Reference Timing Information
Table 8.6 – Reference Timing Information
Symbol
Parameter
Min
Typ
Max
Unit
TRECDET
Time for receiver detection
-
10
-
us
TPHYSTS-RESET
Timing from de-asserting RST_N to the falling
edge of PHYSTS
-
16.7
-
us
TRESET
Reset Assertion Time to GL9714
10
-
-
us



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