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GL9714 Datasheet(PDF) 9 Page - GENESYS LOGIC |
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GL9714 Datasheet(HTML) 9 Page - GENESYS LOGIC |
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9 / 46 page  GL9714 PCI Express TM PIPE x4 PHY ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 9 CHAPTER 2 FEATURES Complies with PCI Express Base Specification rev. 1.1 Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 Integrates quad 2.5 gigabit per second (Gbps) Serializer/Deserializer Supports 8-bit or 10-bit parallel interface @250MHz for x1, x2 and x4 implementation Supports 16-bit parallel interface @125MHz for x1 and x2 configuration Supports DDR configuration for 8-bit or 10-bit mode Beacon transmission and reception Receiver detection Transmission and detection of electrical idle Clock tolerance for 600 ppm in frequencies between bit rates at the two end of a Link On-chip 8-bit/10-bit encoding/decoding and comma alignment On-chip PLL provides clock synthesis 1.8-V power supply for core 2.5-V power supply for IO Above 2.0 kV ESD protection 0.18 µm process Available in LFBGA-233 package |
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