GL9714 datasheet(3/46 Pages) GENESYS

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GL9714 PCI Express

TM PIPE x4 PHY

Page 3

Revision History

Revision

Date

Description

1.00

09/27/2004

First formal release

1.10

04/04/2005

Update for mass production version

1.11

04/12/2005

Revise register description(SW, DEM), p.19

1.12

04/20/2005

1. Add operating current for DC electrical characteristics in Table7.1

2. Correct Power Consumption

1.13

09/20/2005

Modify Package Dimension ,Ch9 , p.39

1.14

10/13/2005

1. Add “Bottom View”, Ch3.1, p.10

2. Change Pin E15 from “TXDK1” to “TXDKA”, Table3.1, p.11

3. Change TXDKA~D type from “O” to “I”, Table3.4, p.15

4. Add a column “I/O Standard”, Table3.4, p.15

5. Change VDDPLL from “C18” to “C8”, Table3.4, p.16

6. Add comment for SCC and OPMODE[1:0], Table3.4 , p.17

1.16

11/15/2005

1. Update Table3.4, p.15~p.17

2. Add Table3.5, p.17

3. Modify the default value of REG0 and REG1 in Table4.1, p.18

4. Modify Ch4.2 Registers Descriptions for REG0 and REG1, p.19

5. Add Ch 4.3, p.21~p.24

6. Update Table 7.5 and Table 7.6 for power consumption, p.36~p.37

7. Change TXDx to RXDx, Figure8.4, p.41

8. The minimum and maximum value of TCYCLE, Table8.2 and Table 8.5, p.42

1.17

12/15/2005

1. Update Table 7.9 for temperature ranges (p.39)

2. Update Table 8.1~8.4 for output delay of RX bus (p.41~p.42)

1.18

03/15/2006

1. Modify the description of OSC25MI and OSC25MO signals, Table 3.4, p.17

2. Update Table 7.1 for deleting IDD1-X4, IDD2-X4, IDD3-X4, IDD1-X2, IDD2-X2, and

IDD3-X2 six items, p.34

3. Update Table 7.9 for deleting the ISUPPLY-1.8 item and adding θJA, ΨJT and θJC

three items, p.39

1.19

03/28/2006

Swap the Pin Out of OSC25MI and OSC25MO in Table 3.1~Table 3.4.

1.20

03/30/2006

Update Table 7.9 for the illustration and the value of thermal parameters, p.39

1.21

04/26/2006

Divide Table 7.9 into Table 7.9(Temperature Range) and Table 7.10(Thermal

Characteristics), p.39

1.22

05/08/2006

Update Fig. 8.1, 8.2 and Table 8.1~8.5 for PIPE input and output timing

characteristic, p.40~p.42

1.23

06/09/2006

Update Table 8.1~8.5 for the description of TCO and TOH, p.41~p.42

1.24

06/20/2006

1.Update Table 3.5 for the parameter of buffer I/O, p.17

2.Remove Table 7.2, p.34

1.25

07/31/2006

1.Remove REN and PLPBK bits of SMBus register REGC, p.20

2.Add REG14 ~ REG17 for SLPBK error count result, p.21

3.Add “PS: Please write “0” to…….” description, p.21

1.26

10/27/2006

Add Duty-H field for Table 8.3 and Table 8.5, p.43

1.30

02/06/2007

Update Table 8.1~8.5 for timing issue, p.42~44

1.31

03/19/2007

1. Add a note to Table 8.1, p.42

2. Update Table 7.4, 7.5 for the power consumption of reference voltage 1.25V,

p37~p38, correct the index of table7.2, 7.3, p35

1.32

04/16/2007

Complies with PCI Express Base Specification rev. 1.1, p9

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