GL9714 datasheet(18/46 Pages) GENESYS

18 / 46 page

GL9714 PCI Express

TM PIPE x4 PHY

Page 18

CHAPTER 4

REGISTERS

There are some registers built-in the GL9714 for test purpose. These registers can be accessed through a serial

bus interface using pin TESTC and TESTD. Registers at Offset 05h ~ 0Bh are for internal test only. Please be

careful to leave them as default values.

4.1 Registers Base Address

Table 4.1 - Base Address for Registers

Mnemonic

Offset

Description

Default

REVID

00h

Revision ID and Auto-calibration Result Register

8’bxxxx0xxx

XCVROPT

01h

Transceiver Option Register

8’hE9

LPBKTEST

02h

BIST and Beacon/Test Data Pattern Register, Part 1

8’h00

BCNPAT2

03h

Beacon/Test Data Pattern Register, Part 2

8’h03

BCNPAT3

04h

Beacon/Test Data Pattern Register, Part 3

8’hFF

05h

For internal test only

06h

For internal test only

07h

For internal test only

08h

For internal test only

09h

For internal test only

0Ah

For internal test only

0Bh

For internal test only

0Ch

Buffer Test Register

8’h00

SLCDT

0Dh

Serial Loopback and Comma Detect Test Register

8’h00

Notation:

R/W

Read / Write

R/O

Read Only

W/O

Write Only

R/W1C

Read / Write “1” to Clear

R/W/C

Read / Write and hardware automatic Clear

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