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GL9714 Datasheet(PDF) 42 Page - GENESYS LOGIC

Part # GL9714
Description  PCI ExpressTM PIPE x4 PHY
PDF  46 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL9714 Datasheet(HTML) 42 Page - GENESYS LOGIC

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GL9714 PCI Express
TM PIPE x4 PHY
©2004-2007 Genesys Logic Inc. - All rights reserved.
Page 42
Figure 8.2 – Definition of Output Timing
Table 8.1 – Input Setup, Hold Time and Output Timing for 8-bit SDR Mode
Symbol
Parameter
Min
Typ
Max
Unit
TCYCLE
PCLK cycle time
3.99
4
4.01
ns
Duty-H
Duty cycle for PCLK high
35
-
50
%
TIS
Input setup time requirement
1
0.8
-
-
ns
TIH
Input hold time requirement
1
1
-
-
ns
TCO
Clock to output delay
2
-
-
3.2
ns
TOH
Output hold time
2
1
-
-
ns
Note:
1. Based on data rise time=1.9ns, fall time=1.3ns, and the slew rate is based on 20%~80% measuring.
2. The test load is 10 pf.
3. All setup, hold and Tco numbers include PCLK jitter and SSO, which is about +/- 250ps.



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