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GL9714 Datasheet(PDF) 24 Page - GENESYS LOGIC |
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GL9714 Datasheet(HTML) 24 Page - GENESYS LOGIC |
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24 / 46 page ![]() GL9714 PCI Express TM PIPE x4 PHY ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 24 Below is a key to the protocol diagrams. S Start Condition Sr Repeated Start Condition Rd Read (bit value of 1) Wr Write (bit value of 0) x Shown under a field indicates that that ` field is required to have the value of ‘x’ A Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK) P Stop Condition Master-to-GL9714 GL9714-to-Master Figure 4.5 – SMBus Packet Protocol Diagram Element Key The first byte of a Write Byte access is the command code. The next one byte is the data to be written. In this example the master asserts GL9714’s address followed by the write bit. GL9714 acknowledges and the master delivers the command code. GL9714 again acknowledges before the master sends the data byte. GL9714 acknowledges the data byte, and the entire transaction is finished with a STOP condition. Figure 4.6 – Write Byte Protocol Reading data is slightly more complicated than writing data. First the host must write a command to GL9714. Then it must follow that command with a repeated START condition to denote a read from GL9714’s address. GL9714 then returns one byte of data. Note that there is no STOP condition before the repeated START condition, and that a NACK signified the end of the read transfer. Figure 4.7 – Read Byte Protocol |
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