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GL9714 Datasheet(PDF) 19 Page - GENESYS LOGIC

Part # GL9714
Description  PCI ExpressTM PIPE x4 PHY
PDF  46 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL9714 Datasheet(HTML) 19 Page - GENESYS LOGIC

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GL9714 PCI Express
TM PIPE x4 PHY
©2004-2007 Genesys Logic Inc. - All rights reserved.
Page 19
4.2 Registers Descriptions
Offset 00h – REVID …………………………………………….………… Default value = 8’bxxxx0xxx
REV3
REV2
REV1
REV0
BY1
RCAL0
RCAL1
RCAL2
R
R
R
R
R
R
R
R
7-4 REV[3:0]
Chip revision code
3 BY1
x1 package
2-0 RCAL[0:2]
Calibration result of on-chip termination resistors
Offset 01h – XCVROPT ……………………………………………..…………. Default value = 8’hE9
SW1
SW0
DEM1
DEM0
BW0
BW1
RDEF
FEVAL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-6 SW[1:0]
Swing control of transmitter output
Output Swing (Differential, peak-to-peak)
00 0.6V
01 0.8V
10 1.0V
11 1.2V
5-4 DEM[1:0]
De-emphasis control of transmitter output
Amount of De-emphasis
00 No de-emphasis
01 -1.6dB
10 -3.5dB
11 -6.0dB
3-2 BW[0:1]
Bandwidth control of clock recovery circuit
Relative Bandwidth
00
1
01
2
10
4
11
Reserved
1 RDEF
Disable calibration of on-chip termination resistors and leave the resistors to
their default value
0 FEVAL
Force calibration of on-chip termination resistors
When RDEF=0, writing a one to
this bit will make the resistors re-calibrated. This
bit is auto-cleared and always read as zero.



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