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IMX91CEC Datasheet(PDF) 2 Page - NXP Semiconductors |
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IMX91CEC Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 100 page ![]() 1 i.MX 91 introduction NXP’s New Secure, Energy-Efficient i.MX 91 Family Expands Linux® Capabilities for Thousands of Edge Applications. The i.MX 91 applications processor features an Arm® Cortex®-A55 running at up to 1.4 GHz and support for modern LPDDR4 memory to enable platform longevity and reliability; dual Gigabit Ethernet for gateway or multi-network segment support; dual USB ports; and the essential I/O for products in smart factory, smart home, smart office, medical device, metering, and cost-optimized system-on-module platforms. The i.MX 91 may be used in applications such as: • EV Charging • Matter-enabled IoT Platforms • Smart Home, Office, and City • Building Automation and Monitoring • Industrial Monitoring and HMI • Portable or small form-factor Medical and Healthcare devices • Audio and Entertainment IoT Table 1. Features Subsystem Features Cortex®-A55 platform One Cortex®-A55 processor operating at up to 1.4 GHz • 32 KB L1 Instruction Cache • 32 KB L1 Data Cache • 256 KB L2 cache • Media Processing Engine (MPE) with Arm® Neon™ technology supporting the Advanced Single Instruction Multiple Data architecture • Floating Point Unit (FPU) with support of the Arm® VFPv4-D16 architecture Supports of 64-bit Arm® v8.2-A architecture Parity/ECC protection on L1 cache, L2 cache, and TLB RAMs Image Sensor Interface (ISI) • Standard pixel formats commonly used in many camera input protocols • Programmable resolutions up to 2K • Image processing for: — Supports one source of up to 2K horizontal resolution — Supports pixel rate up to 200 Mpixel/s • Image down scaling via decimation and bi-phase filtering • Color space conversion • Interlaced to progressive conversions On-chip memory Boot ROM (256 KB) for Cortex®-A55 On-chip RAM (384 KB) Table continues on the next page... NXP Semiconductors IMX91CEC i.MX 91 Application Processors Data Sheet for Commercial Products IMX91CEC All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Preliminary Data Sheet Rev. 2 — 12 November 2024 Preliminary - Subject to Change Without Notice 2 / 100 |
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