IMX91CEC datasheet(46/100 Pages) NXP

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2. Input timing assumes an input signal slew rate of 3 ns (20%/80%).

3. Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm,

unterminated, 5-inch microstrip trace on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the

series resistance in the transmission line should be equal to the selected RDSON of the I/O pad output driver.

4.12.2.3 MII serial management channel timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification.

Figure 27 shows MII asynchronous input timings. Table 48 describes the timing parameters (M10–M15) shown in the figure.

ENET_MDC (output)

ENET_MDIO (output)

M14

M15

M10

M11

M12

M13

ENET_MDIO (input)

Figure 27. MII serial management channel timing diagram

Table 48. MII serial management channel timing1,2,3

Characteristic

Min.

Max.

Unit

M10

ENET_MDC falling edge to ENET_MDIO output invalid (min.

propagation delay)

-1.5

—

M11

ENET_MDC falling edge to ENET_MDIO output valid (max.

propagation delay)

—

M12

ENET_MDIO (input) to ENET_MDC rising edge setup

—

M13

ENET_MDIO (input) to ENET_MDC rising edge hold

—

M14

ENET_MDC pulse width high

40%

60%

ENET_MDC period

M15

ENET_MDC pulse width low

40%

60%

ENET_MDC period

1. The timings assume the following configuration: DSE[5:0] = 001111 and FSEL1[1:0] = 11.

2. Input timing assumes an input signal slew rate of 3 ns (20%/80%).

3. Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm.

Unterminated, 5-inch microstrip trace on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the

series resistance in the transmission line should be equal to the selected RDSON of the I/O pad output driver.

4.12.2.4 RGMII signal switching specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver devices.

NXP Semiconductors

IMX91CEC

i.MX 91 Application Processors Data Sheet for Commercial Products

IMX91CEC

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Preliminary Data Sheet

Rev. 2 — 12 November 2024

Preliminary - Subject to Change Without Notice

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