IMX91CEC datasheet(3/100 Pages) NXP

3 / 100 page

Table 1. Features...continued

Subsystem

Features

External memory interface

16-bit DRAM interface support at up to :

• LPDDR4 with inline ECC

Three Ultra Secure Digital Host Controller (uSDHC) interfaces:

• One eMMC 5.1 (8-bit) compliance with HS400 DDR signaling to support up to 400

MB/sec

• One SDXC (4-bit, no eMMC 5.1, with extended capacity)

• One SDIO (4-bit, SD/SDIO 3.01 compliance with 200 MHz SDR signaling and up

to 100 MB/sec)

FlexSPI Flash with support for XIP (for Cortex®-A55 in low-power mode) and support

for either one Octal SPI or Quad SPI FLASH device. It also supports both Serial NOR

and Serial NAND flash using the FlexSPI.

GPIO and input/output multiplexing

General-purpose input/output (GPIO) modules with interrupt capability

Input/output multiplexing controller (IOMUXC) to provide centralized pad control

Power management

Temperature sensor with programmable trip points

Flexible power domain partitioning with internal power switches to support efficient

power management

Security

Trusted Resource Domain Controller (TRDC)

• Supports 16 domains

Arm® TrustZone® (TZ) architecture, including both TrustZone-A

On-chip RAM (OCRAM) secure region protection using OCRAM controller

EdgeLock® secure enclave

Battery Backed Security Module (BBSM)

• Secure Non-Volatile Storage (SNVS)

• Secure real-time clock (RTC)

System debug

Arm® CoreSight™ debug and trace technology

Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering

Unified trace capability for single core Cortex®-A55

Cross Triggering Interface (CTI)

Support for 4-pin (JTAG) debug interface and SWD

NXP Semiconductors

IMX91CEC

i.MX 91 Application Processors Data Sheet for Commercial Products

IMX91CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 12 November 2024

Preliminary - Subject to Change Without Notice

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