IMX91CEC datasheet(10/100 Pages) NXP

10 / 100 page

2. Thermal test board meets JEDEC specification for this package (JESD51-9).

3. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is

solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not

meant to predict the performance of a package in an application-specific environment.

4. Junction-to-Case thermal resistance determined using an isothermal cold plate.

4.1.3 Power architecture

The power architecture of i.MX 91 is defined based on the assumption that systems are constructed for the case where the PMIC

is used to supply all the power rails to the processor. The SoC may be powered from discrete parts rather than a PMIC, but a

discrete-based solution is not necessarily BOM cost-optimized.

NVCC_BBSM_1P8 must be powered first and stay until the last.

The digital logic inside chip will be supplied with VDD_SOC.

The DRAM controller and PHY have multiple external power supplies: VDD_SOC supplies SoC synthesized DRAM controller

digital logic, VDD_ANAx_0P8 for PLL and PHY digital logic, VDD_ANAx_1P8 for DRAM PLL and PHY analog circuitry, and

VDD2_DDR for 1.1 V DRAM PHY I/O supply.

For all the integrated analog modules, their 1.8 V analog power will be supplied externally through power pads. These supplies

are separated with other power pads (NVCC_XXX) on the package to keep them clean. External filters on these supplies may be

needed on the board to isolate the analog 1.8 V supplies from the noisy I/O NVCC_XXX supplies.

For the integrated USB PHY, its 3.3 V (where supported), 1.8 V, and their digital power will be supplied externally through power

pads. The powers to those PHYs are separated with other power pads on the package to keep them clean. External filters may

be needed to isolate the PHY supplies to keep them clean.

For BBSM/RTC, the 1.8 V I/O pre-driver supply and 1.8 V I/O pad supply will also be supplied externally. The BBSM_LP core digital

domain logic is supplied by an internal LDO.

Figure 3 is the power architecture diagram for the whole chip. Note that it only shows power supplies, and does not show capacitors

that may be required for internal LDO regulators.

NXP Semiconductors

IMX91CEC

i.MX 91 Application Processors Data Sheet for Commercial Products

IMX91CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 12 November 2024

Preliminary - Subject to Change Without Notice

10 / 100

IMX91CEC Datasheet(PDF) 10 Page - NXP Semiconductors