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IMX91CEC Datasheet(PDF) 66 Page - NXP Semiconductors |
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IMX91CEC Datasheet(HTML) 66 Page - NXP Semiconductors |
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66 / 100 page ![]() TCSS TCK T DVO T DHO T DVO T DHO T CSH FLEXSPI_SCLK FLEXSPI_SSx_B FLEXSPI_DATA[7:0] Figure 48. FlexSPI output timing in DDR mode 4.12.10 USB PHY parameters The USB PHY parameters meet the electrical compliance requirements listed as following: • Universal Serial Bus Revision 2.0 Specification (including ECNs and errata), On-The-Go and Embedded Host Supplement to the Universal Serial Bus Revision 2.0 Specification (including ECNs and errata) 4.12.10.1 Pad/Package/Board connections The USBx_VBUS pin cannot directly connect to the 5 V VBUS voltage on the USB2.0 link. Each USBx_VBUS pin must be isolated by an external 30 KΩ 1% precision resistor. The USB 2.0 PHY uses USBx_TXRTUNE and an external resistor to calibrate the USBx_DP/DN 45 Ω source impedance. The external resistor value is 200 Ω 1% precision on each of USBx_TXRTUNE pad to ground. 5 Boot mode configuration This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation. i.MX 91 supports three different boot modes: • Normal Boot Mode • Boot from Internal Fuse Mode • Serial Download Boot Mode Three different boot modes can be either selected via different boot mode pins or overridden by fuses. i.MX 91 supports Single Boot: Cortex-A55 core is in charge of loading all containers and images. For detailed boot mode configuration, see the see the i.MX 91 Fuse Map and the System Boot chapter in i.MX 91 Reference Manual (IMX91RM). 5.1 Boot mode configuration pins There are four boot mode pins used to select boot mode. Table 77. Fuses and associated pins used for boot BOOT_MODE[3:0] Function x000 Boot from Internal Fuses 0001 Serial Download (USB1) Table continues on the next page... NXP Semiconductors IMX91CEC i.MX 91 Application Processors Data Sheet for Commercial Products IMX91CEC All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Preliminary Data Sheet Rev. 2 — 12 November 2024 Preliminary - Subject to Change Without Notice 66 / 100 |
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