IMX91CEC datasheet(21/100 Pages) NXP

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DDRC operation is contingent upon the board’s DDR design adherence to the DDR design and layout requirements stated in the

hardware development guide for the i.MX 91 application processors.

4.6 I/O AC parameters

This section includes the AC parameters of the following I/O types:

• General Purpose I/O (GPIO)

The GPIO load circuit and output transition time waveforms are shown in Figure 5 and Figure 6.

Test Point

From Output

Under Test

CL includes package, probe and fixture capacitance

Figure 5. Load circuit for output

0 V

OVDD

20%

80%

20%

Output (at pad)

Figure 6. Output transition time waveform

4.6.1 DDR I/O AC electrical characteristics

The DDR I/O pads support LPDDR4 operational modes. The DDRC is compliant with JEDEC-compliant SDRAMs.

DDRC operation is contingent upon the board’s DDR design adherence to the DDR design and layout requirements stated in the

hardware development guide for the i.MX 91 application processor.

4.7 Differential I/O output buffer impedance

The Differential CCM interface is designed to be compatible with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits (2001) for details.

4.7.1 DDR I/O output buffer impedance

DDR output driver and ODT impedances are controlled across PVT using ZQ calibration procedure with a 120 ohm ±1% resistor

to ground. Programmable drive strength and ODT impedance targets available in the NXP DDR tool are detailed in the device IBIS

model. Impedance deviation (calibration accuracy) is ±10% (Maximum/Minimum impedance) across PVT.

4.8 System modules timing

This section contains the timing and electrical parameters for the modules in each i.MX 91 processor.

4.8.1 Reset timing parameters

Figure 7 shows the reset timing and Table 23 lists the timing parameters.

POR_B

CC1

(Input)

Figure 7. Reset timing diagram

NXP Semiconductors

IMX91CEC

i.MX 91 Application Processors Data Sheet for Commercial Products

IMX91CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 12 November 2024

Preliminary - Subject to Change Without Notice

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