IMX91CEC datasheet(43/100 Pages) NXP

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Table 45. SDR50/SDR104 interface timing specification (Low drive mode)1,2

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

7.5

—

SD2

Clock Low Time

tCL

3.3

—

SD3

Clock High Time

tCH

3.3

—

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4

uSDHC Output Delay

tOD

-3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

-1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD6

uSDHC Input Setup Time

tISU

2.4

—

SD7

uSDHC Input Hold Time

tIH

1.5

—

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)3

SD8

uSDHC Input Data Window

tODW

0.5 x tCLK

—

1. Input timing assumes an input signal slew rate of 1 ns (20%/80%).

2. Output timing valid for maximum external load CL = 15 pF, which is assumed to be a 10 pF load at the end of a 50 ohm,

unterminated, 2-inch microstrip trace on standard FR4 (3.3 pF/inch). For best signal integrity, the series resistance of the

transmission line should be matched closely to the RDSON of the I/O pad output driver.

3. Data window in SDR100 mode is variable.

4.12.1.6 Bus operation condition for 3.3 V and 1.8 V signaling

Signaling level of SD/eMMC4.5/5.0/5.1 can be 1.8 V or 3.3 V depending on the working mode. The DC parameters for NVCC_SD2

supplies are identical to those shown in General purpose I/O (GPIO) DC parameters.

4.12.1.7 uSDHC supported modes

For SD:

• All SD 3.0 protocols are supported at full speeds on all three SDHC interfaces. This includes DS, HS, SDR12, SDR25, SDR50,

SDR104, and DDR50.

• The maximum supported SDR frequency is 200 MHz which is covered in SDR104 mode, and maximum DDR frequency is

50 MHz as a part of DDR50 mode.

For eMMC:

• eMMC HS400 is only supported on SDHC1 as that is the only one with 8-bit interface.

• eMMC HS200 is supported on all three SDHC interfaces because this protocol supports both a 4-bit mode and an 8-bit mode,

which can work on SDHC2 and SDHC3.

• eMMC High Speed DDR, High Speed SDR, and the less than or equal to 26 MHz MMC legacy protocols are also supported

on all three SDHC interfaces.

NXP Semiconductors

IMX91CEC

i.MX 91 Application Processors Data Sheet for Commercial Products

IMX91CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 12 November 2024

Preliminary - Subject to Change Without Notice

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