IMX91CEC datasheet(26/100 Pages) NXP

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Meeting the necessary timing requirements for a DDR memory system is highly dependent on the components chosen and

the design layout of the system as a whole. NXP cannot cover in this document all the requirements needed to achieve a

design that meets full system performance over temperature, voltage, and part variation; PCB trace routing, PCB dielectric

material, number of routing layers used, placement of bulk/decoupling capacitors on critical power rails, VIA placement, GND

and Supply planes layout, and DDR controller/PHY register settings all are factors affecting the performance of the memory

system. Consult the hardware user guide for this device and NXP validated design layouts for information on how to properly

design a PCB for best DDR performance. NXP strongly recommends duplicating an NXP validated design as much as possible

in the design of critical power rails, placement of bulk/decoupling capacitors and DDR trace routing between the processor and

the selected DDR memory. All supporting material is readily available on the device web page on https://www.nxp.com/products/

processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors:IMX9-PROCESSORS.

Processors that demonstrate full DDR performance on NXP validated designs, but do not function on customer designs, are not

considered marginal parts. Customers bear the responsibility of properly designing the Printed Circuit Board, correctly simulating

and modeling the designed DDR system, and validating the system under all expected operating conditions (temperatures,

voltages) prior to releasing their product to market.

Table 27. i.MX 91 DRAM controller supported SDRAM configurations

Parameter

LPDDR4

Number of Controllers

Number of Channels

Number of Chip Selects

Bus Width

16-bit

Maximum supported data rate

• Low drive mode

1600 MT/s

• Nominal drive mode

2400 MT/s

4.9 Display

This section provides information about display subsystem.

4.9.1 LCD Controller (LCDIF) timing parameters

The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing.

LCDn_CLK

(falling edge capture)

LCDn_CLK

(rising edge capture)

LCDn_DATA[23:00]

LCDn Control Signals

Figure 13. LCD timing

NXP Semiconductors

IMX91CEC

i.MX 91 Application Processors Data Sheet for Commercial Products

IMX91CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 12 November 2024

Preliminary - Subject to Change Without Notice

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