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IMX91CEC Datasheet(PDF) 39 Page - NXP Semiconductors |
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IMX91CEC Datasheet(HTML) 39 Page - NXP Semiconductors |
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39 / 100 page  SD7 SD1 SD5 SD5 SD6 SCK Output from Strobe Input from uSDHC to eMMC eMMC to uSDHC DAT0 DAT1 DAT7 ... DAT0 DAT1 DAT7 ... SD4 SD4 SD3 SD2 Figure 23. HS400 timing Table 40. HS400 interface timing specification (Nominal mode)1,2 ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock frequency fPP 0 200 MHz SD2 Clock low time tCL 2.2 — ns SD3 Clock high time tCH 2.2 — ns uSDHC Output/Card Inputs DAT (Reference to SCK) SD4 Output skew from data of edge of SCK tOSkew1 0.45 — ns SD5 Output skew from edge of SCk to data tOSkew2 0.45 — ns uSDHC Input/Card Outputs DAT (Reference to Strobe) SD6 uSDHC input skew tRQ — 0.45 ns SD7 uSDHC hold skew tRQH — 0.45 ns 1. Input timing assumes an input signal slew rate of 1 ns (20%/80%). 2. Output timing valid for maximum external load CL = 15 pF, which is assumed to be a 10 pF load at the end of a 50 ohm, unterminated, 2-inch microstrip trace on standard FR4 (3.3 pF/inch). For best signal integrity, the series resistance of the transmission line should be matched closely to the RDSON of the I/O pad output driver. Table 41. HS400 interface timing specification (Low drive mode)1,2 ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock frequency fPP 0 133 MHz Table continues on the next page... NXP Semiconductors IMX91CEC i.MX 91 Application Processors Data Sheet for Commercial Products IMX91CEC All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Preliminary Data Sheet Rev. 2 — 12 November 2024 Preliminary - Subject to Change Without Notice 39 / 100 |
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