TMPR4956C datasheet(171/286 Pages) TOSHIBA

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Chapter 11 TX4956 System Interface

11-3

11.2.3

Issue Cycle

Two types of processor issue cycles exist with the TX4956.

•

Processor read request issue cycles.

•

Processor write request issue cycles.

The TX4956 judges the issue cycle of the processor read request by sampling the RdRdy* signal. It

also judges the issue cycle of the processor write request by sampling the WrRdy* signal from the

external agent.

As illustrated in Figure 11.2.2, RdRdy* must be asserted two cycles before the processor read request

address cycle in order to define the address cycle as an issue cycle.

Figure 11.2.2 RdRdy* Signal Status in case of Read Request

As illustrated in Figure 11.2.3, WrRdy* is asserted two cycles before the initial address cycle of the

processor write request, and the address cycle must be defined as the issue cycle.

Figure 11.2.3 WrRdy* Signal Status in case of Write Request

The TX4956 repeats the request address cycle until the conditions of the valid issue cycle are met. If

the processor request is a data transmission, then data transmission starts at the point when the issue cycle

is complete. There is only one issue cycle no matter what the processor request is.

The TX4956 accepts external requests even while trying to issue processor requests. If the external

agent asserts ExtRqst*, the processor responds to the external agent by releasing the system interface and

going into the slave state. Rules relating to the issue cycle of processor requests are strictly applied in

determining the processor run operation as well. The TX4956 performs one of the following:

Address

Issue

Cycle

MasterClock

SysAD Bus

RdRdy*

ValidOut*

Address

Issue

Cycle

MasterClock

SysAD Bus

WrRdy*

ValidOut*

Data

TMPR4956C Datasheet(PDF) 171 Page - Toshiba Semiconductor