TMPR4956C datasheet(172/286 Pages) TOSHIBA

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Chapter 11 TX4956 System Interface

11-4

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Complete issuing of processor requests before external requests are received.

•

Release the system interface and go into the slave mode without completing issuance of the

processor requests.

In the latter of the above situations, the TX4956 issues processor requests after external requests are

complete. Rules relating to issuing are also provided to processor requests.

11.2.4

Handshake Signal

The processor uses the eight control signals explained below to manage the flow of requests.

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RdRdy* and WrRdy* are used by the external agent to indicate that it is ready to accept a new

read or write transaction.

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ExtRqst* and Release* are used to transfer SysAD bus and SysCmd bus control. ExtRqst* is

used by the external agent to indicate the necessity of controlling the interface. Release* is

asserted by the processor when transferring the system interface access privileges.

•

The TX4956 processor uses ValidOut* and the external agent ValidIn* signals to indicate the

valid command/data on the SysCmd/SysAD bus.

11.2.5

System Interface Protocol of R5000 Type

Figure 11.2.4 illustrates the system interface that operates between registers. In other words, processor

output is directly transferred from the output register and changes with the MasterClock rising edge.

Processor input is directly transferred to the input register and the input register latches these input

signals at the rising edge of the MasterClock. In this way, it becomes possible for the system interface to

operate at the fastest clock frequency.

Figure 11.2.4 Operation of the System Interface Between Registers

MasterClock

TX4956

Output data

Input data

TMPR4956C Datasheet(PDF) 172 Page - Toshiba Semiconductor