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TMPR4956C Datasheet(PDF) 176 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 176 Page - Toshiba Semiconductor

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Chapter 11 TX4956 System Interface
11-8
If data have not been returned to the issued processor read request, the applicable request is said
to be “on hold.” This state continues until the requested read data are returned.
The external agent must be able to accept processor read requests at any time if both of the
following two conditions are met.
•
There is no processor read request that is on hold.
•
The RdRdy* signal is asserted for 1 cycle 2 cycles before the issue cycle.
11.2.6.4 Processor write requests
When the processor issues a write request, the specified resources are accessed, then the data are
written to those resources.
Processor write requests are completed when the final data word is transferred to the external
agent.
The external agent must be able to accept processor write requests at any time if either of the two
following conditions are met.
•
There is no processor read request that is on hold.
•
The WrRdy* signal is asserted for 1 cycle 2 cycles before the issue cycle.
11.2.6.5 External requests
As illustrated in Figure 11.2.9, there are three types of external request: read, write, and null.
Figure 11.2.9 External Requests
Read requests are used to call 1-word data from processor internal resources. Write requests are
used to write 1-word data to the processor internal resources. Null requests are requests that do not
require processor operation.
As illustrated in Figure 11.2.10, the processor uses arbitration signals ExtRqst* and Release* to
control the flow of external requests. The external agent cannot issue external requests unless access
privileges to the system interface are obtained. In order to do so, the external agent asserts the
ExtRqst* signal, then waits until the processor asserts the Release* signal for 1 cycle.
External request
• Read
• Write
• Null
TX4956
External agent



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