TMPR4956C datasheet(178/286 Pages) TOSHIBA

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Chapter 11 TX4956 System Interface

11-10

11.2.6.7 External write requests

External write requests can only use the Interrupt register. When the external agent issues a write

request, the Interrupt register is accessed, then the data are written to this register. External write

requests are completed when the data is written to the processor.

11.2.6.8 Read responses

As illustrated in Figure 11.2.11, read responses return data to processor read requests. Read

responses are external requests, strictly speaking, but there is only one difference with other external

requests: read responses do not request permission to use the system interface. Therefore, read

responses are handled separately from other external requests and are simply referred to as read

responses.

Figure 11.2.11 Read Response

11.2.7

Handling of Requests

This section will describe in detail sequences, protocol, and syntax for both processor and external

requests.

•

Load miss

•

Store miss

•

Store hit

•

Cache operation

•

Load Linked/Store Conditional

11.2.7.1 Load miss

If a processor load miss occurs in the primary cache, the processor cannot proceed to the next

process if the cache line that contains the loaded data elements is not received from the external

agent.

If the current cache line set in which the write back bit (W bit) is set is replaced by a new cache

line, the current cache line must be written back.

The processor checks the coherency properties in the TLB entries for pages including the

requested cache lines. If the coherency properties are non-coherent, then a non-coherent read

request is issued. Table 11.2.1 indicates the measures that can be taken when a load miss occurs in

the primary cache.

1. Read request

TX4956

External agent

2. Read response

TMPR4956C Datasheet(PDF) 178 Page - Toshiba Semiconductor