TMPR4956C datasheet(175/286 Pages) TOSHIBA

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Chapter 11 TX4956 System Interface

11-7

11.2.6.2 Processor requests

The term “processor request” refers to either a single request or a series of requests issued via the

system interface in order to access external resources. As illustrated in Figure 11.2.7, there are two

types of processor request: read and write.

Figure 11.2.7 Processor Requests

Read requests are requests that read data from main memory or other memory resources in block,

word, and byte units.

Write requests are requests that write data to main memory or other system resources in block, ,

word, and byte units.

Processor requests are managed by the TX4956 processor in the same manner as the R4000

non-secondary cache mode.

The processor issues requests strictly according to a sequential method. In other words, the

processor cannot issue the next request while a previous request is on hold. For example, after

issuing a read request, the processor waits for a read response before issuing the next request. The

processor only issues write requests when there are no read requests on hold.

When using processor input signals RdRdy* and WrRdy*, the external agent can control the

processor request flow. RdRdy* is the signal that controls the processor read flow, and WrRdy*

controls the processor write request flow. Figure 11.2.8 illustrates the sequence of the processor

request cycle.

Figure 11.2.8 Processor Requests

11.2.6.3 Processor read requests

When the processor issues a read request, the external agent must access the specified resource

and return the requested data.

The external agent returns response data for processor read requests so they can be executed

separately from the requests. In other words, the external agent can start an external request before

returning response data for the processor read request. A processor read request is completed when

the final word of the response data is received from the external agent.

Depending on the data identifier combined with the response data, an error in the response data

may be pointed out. The processor would then treat this error as a bus error.

Processor Request

• Read

• Write

TX4956

External agent

1. Processor issues

read/write requests.

TX4956

External agent

2. External system controls

acceptance of requests

by asserting either

RdRdy* or WrRdy*.

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