TMPR4956C datasheet(223/286 Pages) TOSHIBA

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Chapter 11 TX4956 System Interface

11-55

11.3.13 Data Rate Control

The System interface supports a maximum data rate of one word per cycle, and an external agent may

deliver data to the processor at this maximum data rate. The rate at which data is delivered to the

processor can be controlled by the external agent by driving data and asserting EValid* only when it

wants data to be available.

The processor interprets cycles as valid data cycles when EValid* is asserted and the SysCmd bus

contains a data identifier. The processor continues to accept data until the end of data (EOD) indicator is

received.

The rate at which the processor transmits data to an external agent is programmed in the WBRATE

field in G2S Config register. Data patterns are specified using the letters W and x (W indicates a word size

data cycle and x indicates an unused, or idle, cycle). A data pattern is specified as a sequence of data and

unused cycles that will be repeated to provide the appropriate number of data cycles for a given transfer.

For example, a data pattern of WWxx indicates a data rate of two words every four cycles.

The TX4956 supports two data rates, W and Wxx. During a cycle indicated by an x, the processor

continues to hold the same data as the previous cycle.

A processor block write request for two words with Wxx pattern is illustrated in Figure 11.3.24; this

transaction results from a store doubleword instruction.

Figure 11.3.24 Processor Block Write Request With Wxx Data Rate

SysAD

Cycle

MasterClock

SysCmd

EOK*

PValid*

PMaster*

Data 1

Data 0

Addr

Data 2

Data

Write

Data

TMPR4956C Datasheet(PDF) 223 Page - Toshiba Semiconductor