TMPR4956C datasheet(225/286 Pages) TOSHIBA

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Chapter 11 TX4956 System Interface

11-57

Figure 11.3.28 Consecutive Processor Write Requests Followed By External Write Request

Block Read Maximum Rate

Maximum block reads can occur with the following data rate:

AxW...WxAxW...W (1 cycle between W and A)

where A is the address, W is data (four words, or WWWW, in the data cache miss, and 8 words, or

WWWWWWWW, in an instruction cache miss), and x is an idle cycle.

(When 1 bit of the Mode Register of System Interface (G2SConfig[1]) is set to 1, then 8 words or

WWWWWWWW burst read can occur in an data cache miss.)

Back-to-Back Instruction Cache Misses

With a CPUCLK to MasterClock ratio of 2:1, back-to-back instruction cache misses can be

refilled with the following data rate:

AxWWWWWWWWxxxxxxAxWWWWWWWW (6 cycles between W and A)

That is, the address is followed by an idle cycle, the instruction is executed, six idle cycles occur,

followed by the next address. This pattern is valid for the case in which two sequential instructions

miss in the instruction cache, each instruction residing on a different cache line.

Running completely in uncached space (every instruction is uncached and a cache miss) results in

a similar data pattern:

AxWxxxxxxAxW (6 cycles between W and A)

Back-to-Back Uncached Loads

With a CPUCLK to MasterClock ratio of 2:1, back-to-back uncached doubleword loads have the

following data rate:

AxWWxxxxxxAxWW (6 cycles between W and A)

That is, the address is followed by an idle cycle, a doubleword data (2 words data), six idle cycles,

and the next address.

With a CPUCLK to MasterClock ratio of 2:1, back-to-back uncached word loads have the

following data rate:

AxWxxxxxxAxW

That is, the address is followed by an idle cycle, a word data, six idle cycles, and the next address.

EOD

Data

Write

Addr

Addr1

Addr0

SysAD

Cycle

MasterClock

SysCmd

EReq*

EValid*

EOK*

PValid*

PMaster*

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