TMPR4956C datasheet(271/286 Pages) TOSHIBA

271 / 286 page

Chapter16 FPU Instruction Set Details

16-7

In the following pages, the notation FGR refers to the FPU’s 32 General-Purpose Registers FGRO through

FGR31, and FPR refers to the FPU’s Floating-Point Registers. When the FR bit in the Status register (SR26)

equals zero, only the even Floating-Point Registers are valid and the FPU’s 32 General-Purpose Registers are

32-bits wide. When the FR bit in the Status register (SR26) equals one, both odd and even Floating-Point

Registers may be used and the FPU’s 32 General-Purpose Registers are 64-bits wide.

The following routines are used in the description of the floating-point operations to get the value of an FPR

or to change the value of an FGR:

32 Bit Mode

value < - - ValueFPR (fpr, fmt)

/* undefined for odd fpr */

case fmt of

S, W:

value < - - FGR[fpr

+ 0]

/* undefined for fpr not even */

value < - - FGR[fpr

+ 1]⎥ ⎢FGR[fpr + 0]

end

StoreFPR (fpr, fmt, value):

/* undefined for odd fpr */

case fmt of

S, W:

FGR[fpr

+ 1] < - - undefined

FGR[fpr

+ 0] < - - value

FGR[fpr

+ 1] < - - value63:32

FGR[fpr

+ 0] < - - value31:0

end

64 Bit Mode

value < - - ValueFPR (fpr, fmt)

case fmt of

value < - - FGR[fpr]31:0

D, L:

value < - - FGR[fpr]

end

StoreFPR (fpr, fmt, value):

case fmt of

S, W:

FGR[fpr] < - - undefined

⎥ ⎢value

D, L:

FGR[fpr] < - - value

end

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