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TMPR4956C Datasheet(PDF) 268 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 268 Page - Toshiba Semiconductor

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Chapter16 FPU Instruction Set Details
16-4
Figure 16.3.1 shows the I-Type instruction format used by load and store operations.
I-Type (Immediate)
base
op
offset
ft
6
26
31
5
5
16
21
16
0
25
20
15
where:
op
is a 6-bit operation code
base
is the 5-bit base register specifier
ft
is a 5-bit. source (for stores) or destination (for loads)
FPA register specifier
offset is the 16-bit signed immediate offset
Figure 16.3.1 Load and Store Instruction Format
All coprocessor loads and stores reference aligned word data items. Thus, for word loads and stores, the
access type field is always WORD, and the low-order two bits of the address must always be zero.
For double word loads and stores, the access type field is always DOUBLEWORD, and the low-order three
bits of the address must always be zero.
Regardless of byte-numbering order (endianness), the address specifies that byte which has the smallest
byte-address of all of the bytes in the addressed field. For a Big-endian machine, this is the leftmost byte; for a
Little-endian machine, this is the rightmost byte.



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