TMPR4956C datasheet(267/286 Pages) TOSHIBA

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Chapter16 FPU Instruction Set Details

16-3

•

conversion between fixed-point and floating-point format

•

conversion between single-precision and double-precision floating-point formats

•

floating-point comparision.

These operations satisfy IEEE Standard 754’s requirements for accuracy. Specifically, these operations

obtain a result which is identical to performing the result with infinite precision and then rounding to the

specified format, using the current rounding mode.

Instructions must specify the certain format of their operands. Only the format conversion instructions

support mixed format operations.

16.3 Load and Store Instructions

In the TX49, the instruction immediately following a load may use the contents of the register loaded. In

such cases, the hardware will interlock, requiring additional real cycles, so scheduling load delay slots is still

desirable, although not absolutely required for functional code.

When the FR bit in the Status register equals zero, the Floating-Point General Registers (FGR) are 32-bits

wide. When the FR bit in the Status register equals one, the Floating-Point General Registers (FGR) are 64-bits

wide. The behavior of the load/store instructions in dependent on the width of the FGRs.

In the load/store operation descriptions, the functions listed in Table 16.3.1 are used to summarize the

handling of virtual addresses and physical memory.

Table 16.3.1 Load/Store Common Functions

Function

Meaning

AddressTranslation

Uses the TLB to find the physical address given the virtual address. The function fails and an exception

is taken if the required translation is not present in the TLB.

LoadMemory

Uses the cache and main memory to find the contents of the word containing the specified physical

address. The low-order two bits of the address and the access type field indicates which of each of the

four bytes within the data word need to be returned. If the cache is enabled for this access, the entire

wordis returned and loaded into the cache.

StoreMemory

Uses the cache, write buffer and main memory to store the word or part of word specified as data in the

word containing the specified physical address. The low-order two bits of the address and the access

type field indicates which of each of the four bytes within the data word should be stored.

TMPR4956C Datasheet(PDF) 267 Page - Toshiba Semiconductor