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TMPR4956C Datasheet(PDF) 266 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 266 Page - Toshiba Semiconductor

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Chapter16 FPU Instruction Set Details
16-2
The coprocessor branch on condition true/false instructions can be used to logically negate any predicate.
Thus, the 32 possible conditions require only 16 distinct comparisons, as shown in Table 16.1.2 below.
Table 16.1.2 shows Logical Negation of Predicates by Condition True/False.
Table 16.1.2 Logical Negation of Predicates by Condition True/False
Condition
Relations
Mnemonic
True
False
Code
Greater
Than
Less
Than
Equal
Unordered
Invalid Operation
exception if
unordered
F
T
0
F
F
F
F
No
UN
OR
1
F
F
F
T
No
EQ
NEQ
2
F
F
T
F
No
UEQ
OGL
3
F
F
T
T
No
OLT
UGE
4
F
T
F
F
No
ULT
OGE
5
F
T
F
T
No
OLE
UGT
6
F
T
T
F
No
ULE
OGT
7
F
T
T
T
No
SF
ST
8
F
F
F
F
Yes
NGLE
GLE
9
F
F
F
T
Yes
SEQ
SNE
10
F
F
T
F
Yes
NGL
GL
11
F
F
T
T
Yes
LT
NLT
12
F
T
F
F
Yes
NGE
GE
13
F
T
F
T
Yes
LE
NLE
14
F
T
T
F
Yes
NGT
GT
15
F
T
T
T
Yes
16.2 Instruction Set Summary
16.2.1
Floating-Point Loads, Stores, and Moves
All movement of data between the floating-point coprocessor and memory is accomplished by
coprocessor load and store operations, which reference the floating-point coprocessor’s General-Purpose
Registers. These operations are unformatted; no format conversions are performed and, therefore, no
Floating-Point exceptions occur due to these operations.
Data may also be directly moved between the floating-point coprocessor and the processor by move to
coprocessor and move from coprocessor instructions. Like the floating-point load and store operations,
move to/from operations perform no format conversions and never cause Floating-Point exceptions.
An additional pair of coprocessor registers are available, called Floating-Point Control registers for
which the only data movement operation supported are moves to and from processor General-Purpose
Registers.
16.2.2
Floating-Point Computational Instructions
The floating-point unit’s operation set includes the flowings:
•
floating-point addition
•
floating-point subtraction
•
floating-point multiplication
•
floating-point division
•
floating-point square root



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