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TMPR4956C Datasheet(PDF) 269 Page - Toshiba Semiconductor |
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TMPR4956C Datasheet(HTML) 269 Page - Toshiba Semiconductor |
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269 / 286 page  Chapter16 FPU Instruction Set Details 16-5 16.4 Computational Instructions Computational instructions include all of the arithmetic floating-point operations performed by the FPU. Figure 16.4.1 shows the R-Type instruction format used for computational operations. R-Type (Register) fd fs function COP1 fmt ft 5 6 10 11 15 16 20 21 25 6 26 31 0 5 5 5 5 6 where: COP1 is a 6-bit major operation code fmt is a 5-bit format specifier fs is a 5-bit source1 register ft is a 5-bit source2 register fd is a 5-bit destination register function is a 6-bit function field Figure 16.4.1 Computational Instruction Format Each floating-point instruction can be applied to a number of operand formats. The operand format for an instruction is specified by the 5-bit fmt field; decoding for this field is shown in Table 16.4.1. Table 16.4.1 Format Field Decoding Code Mnemonic Size Format 16 S single Binary floating-point 17 D double Binary floating-point 18 Reserved 19 Reserved 20 W single 32-bit binary fixed-point 21 L longword 64-bit binary fixed-point 22 to 31 Reserved The function indicates which floating-point operation is to be performed. Table 16.4.2 lists all floating-point instructions. |
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