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TMPR4956C Datasheet(PDF) 265 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 265 Page - Toshiba Semiconductor

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Chapter16 FPU Instruction Set Details
16-1
16. FPU Instruction Set Details
16.1 Instruction Formats
There are three basic instruction format types:
•
Immediate instructions (I-Type), which include load and store operations.
•
Register instructions (R-Type), which include the two-and three-register Floating-Point operations.
•
Branch instructions and Move instructions etc.
The instruction description subsections that follow show how the three basic instruction formats above are
used by:
•
Load and store instructions
•
Register transfer instructions
•
Floating-Point Computational instructions
•
Floating-Point branch instructions
Floating-point instructions are mapped onto the coprocessor 1 instructions, defining coprocessor unit
number one (CP1) as the floating-point unit.
Each operation is valid only for certain formats. Implementations may support some of these formats and
operations only through emulation, but only need support combinations that are valid, which are marked with
a V in Table 16.1.1 below.
Table 16.1.1 shows Valid FPU Instruction Formats.
Table 16.1.1 Valid FPU Instruction Formats
Source Format
Operation
Single
Double
Word
Longword
ADD
V
V
R
R
SUB
V
V
R
R
MUL
V
V
R
R
DIV
V
V
R
R
SQRT
V
V
R
R
ABS
V
V
R
R
MOV
V
V
–
–
NEG
V
V
R
R
TRUNC.L
V
V
–
–
ROUND.L
V
V
–
–
CEIL.L
V
V
–
–
LOOR.L
V
V
–
–
TRUNC.W
V
V
–
–
ROUND.W
V
V
–
–
CEIL.W
V
V
–
–
FLOOR.W
V
V
–
–
CVT.S
–
V
V
V
CVT.D
V
–
V
V
CVT.W
V
V
–
–
CVT.L
V
V
–
–
C
V
V
R
R
V: Valid
R: Reserved for future use (if specified, Floating-Point exception (unimplemented instruction exception) occurs.)
–: not supported (if specified, Floating-Point exception (unimplemented instruction exception) occurs.)



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