TMPR4956C datasheet(263/286 Pages) TOSHIBA

263 / 286 page

Chapter 15 CPU Instruction Set Summary

15-11

MAC Function

OPcode

MAC

Function

[5:3]

[2:0]

MADD

MADDU

Key :

This opcode is reserved for future use. An attempt to execute it causes a Reserved Instruction

exception.

γ:

This opcode is reserved for future use. An attempt to execute it causes a Reserved Instruction

exception.

λ:

This opecode indicates an instruction class. The instruction word must be further decoded by

examining additional tables that show the values for another instruction field.

α:

This opcode is a coprocessor operation, not a CPU operation. If the processor state does not

allow access to the specified coprocessor, the instruction causes a Coprocessor Unusable

exception. It is included in the table because it uses a primary opecode in the instruction

encodeing map.

φ:

This opcode is reserved for future use, but does not cause a Reserved Instruction exception in

TX4956 implementations. It is treated as “NOP”.

θ:

This opcode is valid when BC is only selected in COPz rs; In other case, it causes a Reserved

Instruction exception.

ε:

This opcode is valid when the processor is operating either in the Kernel mode or in the 64-bit

non-Kernel (User or Supervisor) mode; In other case, it causes a Reserved Instruction

exception.

TMPR4956C Datasheet(PDF) 263 Page - Toshiba Semiconductor