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TMPR4956C Datasheet(PDF) 259 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 259 Page - Toshiba Semiconductor

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Chapter 15 CPU Instruction Set Summary
15-7
15.3.8
Multiply and Divide Instructions (Table 15.3.8)
Table 15.3.8 Extensions to the ISA: Multiply and Divide Instructions
Instruction
Description
Note
MULT
Multiply (3-operand)
MULTU
Multiply Unsigned (3-operand)
DMULT
Doubleword Multiply (3-operand)
DMULTU
Doubleword Multiply Unsigned (3-operand)
MADD
Multiply and ADD (3-operand)
extended
MADDU
Multiply and ADD Unsigned (3-operand)
extended
15.3.9
Debug Instructions (Table 15.3.9)
Table 15.3.9 Extensions to the ISA: Debug Instructions
Instruction
Description
Note
CTC0
Move Control To Coprocessor 0
CFC0
Move Control From Coprocessor 0
SDBBP
Software Debug Breakpoint
extended
DERET
Debug Exception Return
extended
15.3.10 Other Instructions (Table 15.3.10)
Table 15.3.10 Other Instructions
Instruction
Description
Note
PREF
Prefetch
15.4 Instruction Execution Cycles
Because the TX49/H4 Core employs the high-speed Multiply and Add Calculator (MAC), multiply
instructions, such as MULT, MULTU, DMULT and DMULTU are executed faster. And, TX49/H4 Core is
improved the execution of divide instructions, too.
Instruction
Latency
Repeat (2op/3op)
MULT 2/3 operand
4/4
1/3
MADD 2/3 operand
4/4
1/3
DMULT 2/3 operand
7/7
6/6
DIV
37
36
DDIV
69
68



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