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TMPR4956C Datasheet(PDF) 258 Page - Toshiba Semiconductor |
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TMPR4956C Datasheet(HTML) 258 Page - Toshiba Semiconductor |
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258 / 286 page ![]() Chapter 15 CPU Instruction Set Summary 15-6 15.3.6 Coprocessor Instructions (Table 15.3.6) Coprocessor instructions invoke coprocessor operations. The format of these instructions depends on which coprocessor is used. Table 15.3.6 CPU Instruction Set: Coprocessor Instructions Instruction Description Note LWCz Load Word to Coprocessor z (z = 1, 2) MIPS I SWCz Store Word from Coprocessor z (z = 1, 2) MIPS I MTCz Move To Coprocessor z (z = 1, 2) MIPS I MFCz Move From Coprocessor z (z = 1, 2) MIPS I CTCz Move Control To Coprocessor z (z = 1, 2) MIPS I CFCz Move Control From Coprocessor z (z = 1, 2) MIPS I COPz Coprocessor Operation z (z = 1, 2) MIPS I BCzT Branch on Coprocessor z True (z = 0, 1, 2) MIPS I BCzF Branch on Coprocessor z False (z = 0, 1, 2) MIPS I BCzTL Branch on Coprocessor z True Likely (z = 0, 1, 2) MIPS II BCzFL Branch on Coprocessor z False Likely (z = 0, 1, 2) MIPS II LDCz Load Double Coprocessor z (z = 1, 2) MIPS III SDCz Store Double Coprocessor z (z = 1, 2) MIPS III DMTCz Doubleword Move To Coprocessor z (z = 1, 2) MIPS III DMFCz Doubleword Move From Coprocessor z (z = 1, 2) MIPS III 15.3.7 CP0 Instructions (Table 15.3.7) Coprocessor 0 instructions are used for operations involving the system control coprocessor (CP0) registers, processor memory management and exception handling. Table 15.3.7 Instruction Set: CP0 Instructions Instruction Description Note MTC0 Move To CP0 MIPS I MFC0 Move From CP0 MIPS I DMTC0 Doubleword Move To CP0 MIPS III DMFC0 Doubleword Move From CP0 MIPS III TLBR Read Indexed TLB Entry TLBWI Write Indexed TLB Entry TLBWR Write Random TLB Entry TLBP Probe TLB for Matching Entry CACHE Cache MIPS III ERET Exception Return MIPS III WAIT Enter power management mode |
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