BM83 datasheet(45/76 Pages) MICROCHIP

45 / 76 page

Notes:

This table reflects the default IO assignment for the turn-key solution. The GPIOs are user configurable.

GPIO P3_4 is used to enter Test mode during reset. If the user wants to use this pin to control external

peripherals, care must be taken to ensure this pin is not pulled LOW and accidentally enters Test mode.

Microchip recommends to reserve UART port (P8_5 and P8_6) for Flash download in Test mode during

production.

Currently, GPIOs ports P8_5 and P8_6 APIs (button detect driver) are not implemented.

6.5

I2S Interface

The BM83 module provides an I2S digital audio input, output or input/output interface to connect with the external

codec or DSP. It provides 8, 16, 44.1, 48, 88.2, and 96 kHz sampling rates for 16-bit and 24-bit data formats. The

following are the BM83 module interface signals:

• MCLK1 – Master Clock (BM83 output)

• SCLK1– Serial/Bit Clock (BM83 input/output)

• DR1 – Receive Data (BM83 input)

• RFS1 – Receive Frame Sync (BM83 input/output)

• DT1 – Transmit Data (BM83 output)

Note: The I2S parameters can be configured by using the Config Tool.

I2S supports the following modes:

• Master mode

– The BM83 serves as a master to provide clock and frame synchronous signals for the master/slave data

synchronizations, as illustrated in the following figures. The MCLK is optional and is not required if the

external I2S device can drive its system clock on its own.

Figure 6-6. BM83 Module in I2S Master Mode

External DSP/

Codec

BCLK

DACLRC

ADCDAT

DACDAT

SCLK1

RFS1

DR1

DT1

BM83

MCLK

MCLK1

• Slave mode

– The BM83 serves as a slave to receive clock and frame synchronous signals from the external codec or

DSP devices, as illustrated in the following figure.

BM83

Application Information

Datasheet

DS70005402C-page 45

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