BM83 datasheet(63/76 Pages) MICROCHIP

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Figure 9-2. Timing Diagram for PCM Modes (Master/Slave)

Left channel

SCLK1

RFS1

Word length

DR1/DT1

Right channel

Bn-1 Bn-2

B1 Bn Bn-1 Bn-2

B1 Bn

1/fs

The following figure illustrates the timing diagram of the audio interface.

Figure 9-3. Audio Interface Timing Diagram

SCLK1

RFS1

DR1

tSCLKCH

tSCLKCL

tSCLKCY

tDH

tRFSH

tRFSSU

The following table provides the timing specifications of the audio interface.

Table 9-13. Audio Interface Timing Specifications (1)

Parameter

Symbol

Min.

Typ.

Max.

Unit

SCLK1 duty ratio

dSCLK

—

SCLK1 cycle time

tSCLKCY

—

SCLK1 pulse width high

tSCLKCH

—

SCLK1 pulse width low

tSCLKCL

—

RFS1 setup time to SCLK1 rising edge

tRFSSU

—

RFS1 hold time from SCLK1 rising edge

tRFSH

—

DR1 hold time from SCLK1 rising edge

tDH

—

Test Conditions: Slave mode, fs = 48 kHz, 24-bit data, and SCLK1 period = 256 fs.

BM83

Electrical Specifications

Datasheet

DS70005402C-page 63

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