TSC2014IYZGR datasheet(18/62 Pages) TI2

18 / 62 page

FS=Full-ScaleVoltage=V

REF

(1)

1LSB=V

/4096

REF

(1)

1LSB

11...111

11...110

11...101

00...010

00...001

00...000

1LSB

InputVoltage

(V)

(2)

TSC2014

SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016

www.ti.com

Product Folder Links: TSC2014

Submit Documentation Feedback

Feature Description (continued)

7.3.4.1 Data Format

The TSC2014 output data are in Straight Binary format as shown in Figure 20. This figure shows the ideal output

code for the given input voltage and does not include the effects of offset, gain, or noise.

(1)

Reference voltage at converter: +REF – (–REF). See Figure 19.

(2)

Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 19.

Figure 20. Ideal Input Voltages and Output Codes

7.3.4.2 Reference

The TSC2014 uses an external voltage reference that applied to the VREF pin. It is possible to use VDD as the

reference voltage because the upper reference voltage range is the same as the supply voltage range.

7.3.4.3 Variable Resolution

The TSC2014 provides either 10-bit or 12-bit resolution for the A/D converter. Lower resolution is often practical

for measuring slow changing signals such as touch pressure. Performing the conversions at lower resolution

reduces the amount of time it takes for the A/D converter to complete its conversion process, which also lowers

power consumption.

7.3.4.4 Conversion Clock and Conversion Time

The TSC2014 contains an internal clock (oscillator) that drives the internal state machines that perform the many

functions of the part. This clock is divided down to provide a conversion clock for the A/D converter. The division

ratio for this clock is set in the A/D Converter Control register (see Table 14). The ability to change the

conversion clock rate allows the user to choose the optimal values for resolution, speed, and power dissipation. If

the 4MHz (oscillator) clock is used directly as the A/D converter clock (when CL[1:0] = (0,0)), the A/D converter

resolution is limited to 10 bits. Using higher resolutions at this speed does not result in more accurate

conversions. 12-bit resolution requires that CL[1:0] is set to (0,1) or (1,0).

Regardless of the conversion clock speed, the internal clock runs nominally at 3.8MHz at a 3V supply (VDD) and

slows down to 3.6MHz at a 1.6V supply. The conversion time of the TSC2014 depends on several functions.

While the conversion clock speed plays an important role in the time it takes for a conversion to complete, a

certain number of internal clock cycles are needed for proper sampling of the signal. Moreover, additional times

(such as the panel voltage stabilization time), can add significantly to the time it takes to perform a conversion.

Conversion time can vary depending on the mode in which the TSC2014 is used. Throughout this data sheet,

internal and conversion clock cycles are used to describe the amount of time that many functions take. These

times must be taken into account when considering the total system design.

TSC2014IYZGR Datasheet(PDF) 18 Page - Texas Instruments

TSC2014IYZGR Datasheet(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL