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TSC2014IYZGR Datasheet(PDF) 8 Page - Texas Instruments |
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TSC2014IYZGR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 62 page  8 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: TSC2014 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated (1) Refer to Figure 36. (2) For capacitive bus loads between 100pF and 400pF, the rise and fall time values must be linearly interpolated. 6.8 Timing Requirements for Figure 2: I 2C High-Speed Mode (f SCL = 1.7 MHz) All specifications typical at –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted. TWO-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT Reset low time(1) tWL(RESET) VDD ≥ 1.6V 10 μs 1.2V ≤ VDD < 1.6V 13 μs SCL clock frequency fSCL 1.7 MHz Hold time (repeated) START condition tHD, STA 160 ns Low period of SCL clock tLOW 320 ns High period of the SCL clock tHIGH 120 ns Setup time for a repeated START condition tSU, STA 160 ns Data hold time tHD, DAT 0 150 ns Data setup time tSU, DAT 10 ns Rise time of SCL signal tRCL Cb = total bus capacitance (2) 20 80 ns Rise time of SDA signal tRDA Cb = total bus capacitance (2) 20 160 ns Fall time of SCL signal tFCL Cb = total bus capacitance (2) 20 80 ns Fall time of SDA signal tFDA Cb = total bus capacitance (2) 1 160 ns Rise time of SCL signal after a repeated START condition and after an acknowledge bit tRCL1 Cb = total bus capacitance (2) 20 160 ns Setup time for STOP condition tSU, STO 160 ns Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 400 pF Pulse width of spike suppressed tSP 0 10 ns (1) Because of the low supply voltage of 1.2V and the wide temperature range of –40°C to +85°C, the I2C system devices may not reach the maximum specification of I2C High-Speed mode, and fSCL may not reach 3.4MHz. (2) Refer to Figure 36. (3) Capacitive load from 10pF to 100pF. 6.9 Timing Requirements for Figure 2: I 2C High-Speed Mode (f SCL = 3.4 MHz) All specifications typical at –40°C to +85°C, VDD = +1.2V (1) to +3.6V, unless otherwise noted. TWO-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT Reset low time(2) tWL(RESET) VDD ≥ 1.6V 10 μs 1.2V ≤ VDD < 1.6V 13 μs SCL clock frequency fSCL 3.4 MHz Hold time (repeated) START condition tHD, STA 160 ns Low period of SCL clock tLOW 160 ns High period of the SCL clock tHIGH 60 ns Setup time for a repeated START condition tSU, STA 160 ns Data hold time tHD, DAT 0 70 ns Data setup time tSU, DAT 10 ns Rise time of SCL signal tRCL Cb = total bus capacitance (3) 10 40 ns Rise time of SDA signal tRDA Cb = total bus capacitance (3) 10 80 ns Fall time of SCL signal tFCL Cb = total bus capacitance (3) 10 40 ns Fall time of SDA signal tFDA Cb = total bus capacitance (3) 1 80 ns Rise time of SCL signal after a repeated START condition and after an acknowledge bit tRCL1 Cb = total bus capacitance (3) 10 80 ns Setup time for STOP condition tSU, STO 160 ns Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 100 pF Pulse width of spike suppressed tSP 0 10 ns |
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