TSC2014IYZGR datasheet(25/62 Pages) TI2

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8-BitMasterCode00001xxx

IfPthen

FastorStandardMode

IfSr(dottedlines)

thenHigh-SpeedMode

2to5

SDA

SCL

SDA

SCL

=CurrentSourcePull-Up

=ResistorPull-Up

A=Acknowledge(SD LOW

)

N=NotAckno ledge

(SDAHIGH)

START

Condition

P=STOP Con iion

d t

Sr=RepeatedSTAR Cond

iti n

High-SpeedMode

FastorStandardMode

Sr P

7-BitSlaveAddress

nx(8-BitDATA

A/N)

TSC2014

www.ti.com

SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016

Product Folder Links: TSC2014

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Device Functional Modes (continued)

7.4.1.2 I2C High-Speed Mode (Hs Mode)

Serial data transfer format in High-Speed (Hs) mode meets the Fast or Standard (F/S) mode I2C bus

specification. Hs mode can only commence after the following conditions (all of which are in F/S mode) exist:

1. START condition (S)

2. 8-bit master code (00001xxx)

3. not-acknowledge bit (N)

Figure 24 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for

triggering Hs mode, and are not to be used for slave addressing or any other purpose. The master code

indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the

Hs mode specification. Because no device is allowed to acknowledge the master code, the master code is

followed by a not-acknowledge bit (N).

After the not-acknowledge bit (N) and SCL have been pulled up to a HIGH level, the master switches to Hs-mode

and enables (at time tH; shown in Figure 24) the current-source pull-up circuit for SCL. Because other devices

can delay the serial transfer before tH by stretching the LOW period of SCL, the master enables its current-

source pull-up circuit when all devices have released SCL, and SCL has reached a HIGH level, thus speeding up

the last part of the rise time of the SCL.

The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit

address, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) condition

and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pull-up

circuit. This disabling enables other devices to delay the serial transfer by stretching the LOW period of SCL. The

master re-enables its current-source pull-up circuit again when all devices have released, and SCL reaches a

HIGH level, which speeds up the last part of the SCL signal rise time.

Data transfer continues in Hs mode after the next repeated START (Sr), and only switches back to F/S mode

after a STOP condition (P). To reduce the overhead of the master code, it is possible that a master links a

number of Hs mode transfers, separated by repeated START conditions (Sr).

Figure 24. Complete High-Speed Mode Transfer

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