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TSC2014IYZGR Datasheet(PDF) 34 Page - Texas Instruments |
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TSC2014IYZGR Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 62 page ![]() WriteCycle I CSlaveAddress 2 I C 2 Write- AddressingByte ACK STOP (1) START 1 C3 C2 C1 C0 RM ControlByte1 A A S P 0 1 7 8 I C 2 SlaveAddress I CWrite- AddressingByte 2 ACK STOP (1) STOP (1) 0 0 A3 A2 A1 A0 ControlByte0 DataByte1/2 (HIGHByte) DataByte2/2 (LOWByte) A A A A P S 0 1 7 I C 2 SlaveAddress I CWrite- AddressingByte 2 MixedM(ControlByte1orControlByte0withReadBit) PlusN(ControlByte0withDataBytes),SeparatedbyTSC ACKs (M+Nx3)x8 A A A A P S 0 1 7 8 8 8 ConverterFunction Select TSCInternalRegisterAddressforWriteData I C 2 SlaveAddress I CWrite- AddressingByte 2 ACK STOP (1) 0 1 A3 A2 A1 A0 ControlByte0 A A P S 0 1 7 8 TSCInternalRegisterStartingAddressmh (2) START START START FromMastertoSlave A=Acknowledge(SDALOW) N=NotAcknowledge(SDAHIGH) S=STARTCondition P=STOPCondition Sr=RepeatedSTARTCondition FromSlavetoMaster NOTES: (1)Inordertostartthenextsequence,aSTOPconditionmustbefollowedbyaSTARTcondition.IfnoSTOPis used,thenaRepeatedSTARTmustbeused.AlsonotethatisaSTOPconditionisissuedinHigh-Speed mode,themodewillreverttothepreviousmode:FastorStandard. (2)mhisahexadecimalnumber. 34 TSC2014 SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: TSC2014 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated 7.5.2 Start A Write Cycle A write cycle begins when the master issues the slave address to the TSC2014. The slave address consists of seven address bits and a write bit (R/W = 0; see Table 5). When the eighth bit has been received and the address matches the AD0 address input pin setting, the TSC2014 issues an acknowledge bit by pulling SDA low for one additional clock cycle (ACK = 0); see Figure 32. When the master receives the acknowledge bit from the TSC2014, the master writes the input control byte to the slave; see Table 5. After the control byte is received by the slave, the slave issues another acknowledge bit by pulling SDA low for one clock cycle (ACK = 0). The master then ends the write cycle by issuing a STOP or repeated START condition; see Figure 33. Figure 33. Write Cycle |
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