TSC2014IYZGR datasheet(23/62 Pages) TI2

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TSC2014

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SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016

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Device Functional Modes (continued)

Figure 23 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two

types of data transfer are possible:

1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the

slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave

address and each received byte.

2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is

transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are

transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other

than the last byte. At the end of the last received byte, a not-acknowledge is returned.

The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer ends

with a STOP condition or a repeated START condition. Because a repeated START condition is also the

beginning of the next serial transfer, the bus will not be released.

The TSC2014 may operate in the following two modes:

1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is

received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning

and end of a serial transfer. Address recognition is performed by hardware after reception of the slave

address and direction bit.

2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver

mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data are

transmitted on SDA by the TSC2014 while the serial clock is input on SCL. START and STOP conditions are

recognized as the beginning and end of a serial transfer.

7.4.1.1 I2C Fast or Standard Mode (F/S Mode)

In I2C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Timing Information

section.

In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a

START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has

finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition

on SDA while SCL is high, as shown in Figure 23. The bus is free for another transmission after a stop condition

has occurred. Figure 23 shows the complete F/S mode transfer on the I2C, two-wire serial interface. The address

byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA state is

only allowed to change while SCL is low, except for the START and STOP conditions. Data are transmitted in 8-

bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word plus

acknowledge bit).

TSC2014IYZGR Datasheet(PDF) 23 Page - Texas Instruments