TSC2014IYZGR datasheet(37/62 Pages) TI2

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RESET

State

Nor a

m l

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t o

Resetting

InitialCondition

<5 s

WL(RESET)

TSC2014

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SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016

Product Folder Links: TSC2014

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7.5.4 Register Reset

There are three way to reset the TSC2014.

•

First: At power-on, a power good signal generates a prolonged reset pulse internally to all registers.

•

Second: An external pin, RESET, is available to perform a system reset or allow other peripherals (such as a

display) to reset the device if the pulse meets the timing requirement (at least 10μs wide). Any RESET pulse

less than 5μs will be rejected. To accommodate the timing drift between devices because of process

variation, a RESET pulse width between 5μs to 10μs falls into the gray area that is not recognized, and the

result is undetermined; this situation should be avoided. Refer to Figure 36 for details. A good reset pulse

must be low for at least 10 μs. There is an internal spike filter to reject spikes up to 20ns wide.

NOTE: See Timing Requirements for more information.

Figure 36. External Reset Timing

•

Third: A software reset can be activated by writing a '1' to CB1.1 (bit 1 of control byte 1). It should be noted

this reset is not self-clearing so the user must write a '0' to remove the software reset.

A reset clears all registers and loads default values. A power-on reset and external (hardware) reset take

precedence over a software reset. If a software reset is not cleared by the user, it is cleared by either a power-on

reset or an external (hardware) reset.

NOTE

It is required to have the host issue a hardware reset to the TSC2014 after the device

power is good and stable to ensure all the registers initialized properly.

7.6 Register Maps

7.6.1 R/W

internally as the starting address for a register read (see Figure 33). The content of the addressed register is sent

to SDA by using I2C read addressing (see Figure 34 and Figure 35). A '0' indicates that the data following

Control Byte 0 on SDA are written into the internal register addressed by bits A3-A0 (see Figure 33).

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