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TSC2014IYZGR Datasheet(PDF) 44 Page - Texas Instruments

Part # TSC2014IYZGR
Description  TSC2014 1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire Touch Screen Controller with I2C™ Interface
PDF  62 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TSC2014IYZGR Datasheet(HTML) 44 Page - Texas Instruments

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TSC2014
SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: TSC2014
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
7.6.4.1.6
PR2-PR0
Precharge time selection. These bits set the amount of time allowed for precharging any pin capacitance on the
touch screen prior to sensing if a pen touch is happening.
Table 16. Precharge Time Selection
PR2
PR1
PR0
PRECHARGE TIME(tPRE)
0
0
0
20μs
0
0
1
84μs
0
1
0
276μs
0
1
1
340μs
1
0
0
1.044ms
1
0
1
1.108ms
1
1
0
1.300ms
1
1
1
1.364ms
7.6.4.1.7
SNS2-SNS0
Sense time selection. These bits set the amount of time the TSC2014 waits to sense whether the screen is
touched after converting a coordinate.
Table 17. Sense Time Selection
SNS2
SNS1
SNS0
SENSE TIME (tSNS)
0
0
0
32μs
0
0
1
96μs
0
1
0
544μs
0
1
1
608μs
1
0
0
2.080ms
1
0
1
2.144ms
1
1
0
2.592ms
1
1
1
2.656ms
7.6.4.1.8
DTW
Detection of pen touch in wait (patent pending). Writing a '1' to this bit enables the pen touch detection in the
background while waiting for the host to issue the converter function in host-initiated/controlled modes. This
background detection allows the TSC2014 to pull high at PINTDAV to indicate no pen touch detected while
waiting for the host to issue the converter function. If the host polls a high state at PINTDAV before the convert
function is sent, the host can abort the issuance of the convert function and stay in the polling PINTDAV mode
until the next pen touch is detected.
7.6.4.1.9
LSM
Longer sampling mode. When this bit is set to '1', the extra 500ns of sampling time is added to the normal
sampling cycles of each conversion. This additional time is represented as approximately two internal oscillator
clock cycles. For VDD = 1.2V at –40°C, the LSM bit should be set to '1' so that the sampled signal has enough
time to settle.



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