Register

[HEX]

Register Name

Read/Write

POR Default

[HEX]

GENERAL PURPOSE REGISTERS

1A

General Purpose Input

Read Only

See (1)

1B

General Purpose Output

R/W

See (2)

[RESERVED] REGISTERS—NOT USED

06

Not Used

N/A

N/A

0C

Not Used

N/A

N/A

15

Not Used

N/A

N/A

17

Not Used

N/A

N/A

18

Not Used

N/A

N/A

1C–1F

Not Used

N/A

N/A

20

Not Used

N/A

N/A

22–2F

Not Used

N/A

N/A

30–3F

Not Used

N/A

N/A

40–45

Not Used

N/A

N/A

4E

Not Used

N/A

N/A

60–BE

Not Used

N/A

N/A

C0–FD

Not Used

N/A

N/A

(1)

For Register 0x1A the Power-On-Reset for the five LSB's are the logic states present on the 5 GPIOx pins.

(2)

For Register 0x1B the Power-On-Reset for the five LSB's are the logic states present on the 5 GPDx pins.

7.1.3 LM64 Initial Register Sequence and Register Descriptions in Functional Order

The following is a Register Map grouped in functional and sequence order. Some address locations have been

left blank to maintain compatibility with LM86. Addresses in parenthesis are mirrors of named address for

backwards compatibility with some older software. Reading or writing either address will access the same 8-bit

register.

7.1.3.1 LM64 Required Initial Fan Control Register Sequence

Important! The BIOS must follow the sequence below to configure the following Fan Registers for the LM64

before using any of the Fan or Tachometer or PWM registers:

Step

[Register]HEX and Setup Instructions(1)

1

[4A] Write bits 0 and 1; 3 and 4. This includes tach settings if used, PWM internal clock select (1.4 kHz or 360 kHz) and PWM

Output Polarity.

2

[4B] Write bits 0 through 5 to program the spin-up settings.

3

[4D] Write bits 0 through 4 to set the frequency settings. This works with the PWM internal clock select.

4

Choose, then write, only one of the following:

A. [4F–5F] the Lookup Table, or

B. [4C] the PWM value bits 0 through 5.

5

If Step 4A, Lookup Table, was chosen and written then write [4A] bit 5 = 0.

(1)

All other registers can be written at any time after the above sequence.

LM64

SNAS207B – MAY 2004 – REVISED JANUARY 2024

www.ti.com

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