LM76005 datasheet(26/51 Pages) TI2

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ΔVOUT-C = ΔiL / (8 × fSW × COUT)

(19)

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the

sum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage

regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens,

output capacitors provide the required charge before the inductor current can slew to the appropriate level. The

initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until

the control loop response increases or decreases the inductor current to supply the load. To maintain a small

overshoot or undershoot during a transient, small ESR, and large capacitance are desired. But these also come

with higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output

voltage deviation.

For a given input and output requirement, Equation 20 gives an approximation for an absolute minimum output

cap required:

OUT

(1 D )

(1 r)

/ I

)

¨¨

u u '

(20)

Along with this for the same requirement, calculate the maximum ESR as per Equation 21:

OUT

D '

ESR <

+ 0.5

u ¨

(21)

where

• r = ripple ratio of the inductor ripple current (ΔiL / IOUT)

• ΔVO = target output voltage undershoot

• D’ = 1 – duty cycle

• fSW = switching frequency

• IOUT = load current

A general guideline for COUT range is that COUT must be larger than the minimum required output capacitance

calculated by Equation 20. Limit the maximum value of total output capacitance to between 800 μF and 1200 μF.

Large values of output capacitance can prevent the regulator from starting up correctly and adversely effect the

loop stability. If values greater than the given range are to be used, then a careful study of start-up at full load

and loop stability must be performed.

In applications with VOUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This limits

potential output voltage overshoots as the input voltage falls below the device normal operating range. To

optimize the transient behavior a feedforward capacitor can be added in parallel with the upper feedback

resistor. For this design example, three 47-µF, 10-V, X7R ceramic capacitors are used in parallel.

8.2.2.7 Feedforward Capacitor

The LM76005 is internally compensated. Depending on the VOUT and frequency FS, if the output capacitor COUT

is dominated by low ESR (ceramic types) capacitors, it can result in low phase margin. To improve the phase

boost an external feedforward capacitor, CFF can be added in parallel with RFBT. CFF is chosen such that phase

margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover frequency

without CFF (fx) is shown in Equation 22, assuming COUT has very small ESR.

OUT

15.46

(22)

Equation 23 for CFF was tested:

LM76005

SNVSBK5A – FEBRUARY 2020 – REVISED JULY 2020

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