LM76005 datasheet(35/51 Pages) TI2

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10 Layout

10.1 Layout Guidelines

The performance of any switching converter depends as much upon the layout of the PCB as the component

selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and

minimum generation of unwanted EMI.

1. Place ceramic high frequency bypass CIN as close as possible to the LM76005 PVIN and PGND pins.

Grounding for both the input and output capacitors must consist of localized top-side planes that connect to

the PGND pins and PAD.

2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device

ground.

3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB, must be located close to the FB

pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense

is made at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer on the

other side of a shielding layer.

4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path. Have a single

point ground connection to the plane. Route the ground connections for the feedback, soft start, and enable

components to the ground plane. This prevents any switched or load currents from flowing in the analog

ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output

voltage ripple behavior.

5. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

6. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the

ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be

connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking

to keep the junction temperature below 125°C.

10.1.1 Layout Highlights

1. Minimize the area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize

the high di/dt paths during PC board layout as shown in the figure above. The high current loops that do not

overlap have high di/dt content that causes observable high frequency noise on the output pin if the input

capacitor CIN is placed at a distance away from the LM76005. Therefore, place CIN as close as possible to

the LM76005 PVIN and PGND pins. This minimizes the high di/dt area and reduce radiated EMI. Additionally,

grounding for both the input and output capacitor must consist of a localized top-side plane that connects to

the PGND pin.

2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components

must be routed to the AGND pin of the device. This prevents any switched or load currents from flowing in the

analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic

output voltage ripple behavior.

3. Minimize trace length to the FB pin net. Place both feedback resistors, RFBT and RFBB, close to the FB pin.

Because the FB node is high impedance, maintain the copper area as small as possible. Route the traces

from RFBT, RFBB away from the body of the LM76005 to minimize possible noise pickup. Place Cff directly in

parallel with RFBT.

4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or

output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a

separate feedback voltage sense trace is made to the load. Doing so corrects for voltage drops and provide

optimum output accuracy.

5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the

ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be

connected to inner layer heat-spreading ground planes. For best results use a 10 × 10 via array (or greater)

with a minimum via diameter of 12 mil thermal vias spaced 46.8 mil apart. Ensure enough copper area is

used for heat-sinking to keep the junction temperature below 125°C.

www.ti.com

LM76005

SNVSBK5A – FEBRUARY 2020 – REVISED JULY 2020

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