LM76005 datasheet(27/51 Pages) TI2

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FBT

FBB

2 f

/ /R

)

(23)

If capacitors with high ESR are used, CFF is not required. The CFF capacitor creates a time constant with RFBT

that couples the attenuated output voltage ripple to the FB node. Using a value that is too large for CFF can

couple too much ripple to FB node and affect output voltage regulation. For capacitors with medium ESR (20 –

200 mΩ), Equation 1 can be used as a quick starting point. For the application in this design example, a 47-pF

C0G capacitor is used.

8.2.2.8 Bootstrap Capacitors

Every LM76005 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.47 μF

and rated at 6.3 V or greater. The bootstrap capacitor is located between the SW pin and the BOOT pin. The

bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature

stability.

For improved EMI performance, a boot resistor can be added in series with the bootstrap capacitor. The boot

resistor will slow down the rising edge of the switch node.

8.2.2.9 VCC Capacitors

The VCC pin is the output of an internal LDO for LM76005. The input for this LDO comes from either VIN or

BIAS (please refer to functional block diagram for LM76005). To ensure stability of the part, place a 1-µF to 2.2-

µF, 10-V capacitor for this pin. Never short VCC pin to ground during operation.

8.2.2.10 BIAS Capacitors

For an output voltage of 3.3 V and greater, connect the BIAS pin to the output to increase light load efficiency.

The BIAS pin is one of the two inputs for the VCC LDO. When BIAS voltage is below VBIAS-ON threshold, the

input for the VCC LDO is internally connected to VIN. Because this is an LDO, the voltage differences between

the input and output affects the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be

added close to the BIAS pin as an input capacitor for the LDO.

8.2.2.11 Soft-Start Capacitors

The SS pin can be left floating, and the LM76005 implements a soft-start time of 6.3 ms. To use an external soft-

start capacitor, the capacitor must be sized so that the soft-start time is greater than 6.3 ms. Use Equation 24 to

calculate the soft-start capacitor value:

CSS = ISSC × tSS

(24)

With a desired soft-start time of 11 ms, a soft-start charging current of 2 µA, and an internal VREF of 1 V,

Equation 24 yields a soft-start capacitor value of 22 nF.

8.2.2.12 Undervoltage Lockout Setpoint

The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. RENT

is connected between the PVIN pin and the EN pin of the LM76005. RENB is connected between the EN pin and

the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power

down or brownouts when the input voltage is falling. Equation 25 can be used to determine the VIN UVLO level.

VIN-UVLO-RISING = VENH × (RENB + RENT) / RENB

(25)

The EN rising threshold (VENH) for LM76005 is set to be 1.204 V (typical). Choose the value of RENB to be 100

kΩ to minimize input current from the supply. If the desired VIN UVLO level is at 5 V, then the value of RENT can

be calculated using Equation 26:

RENT = (VIN-UVLO-RISING / VENH – 1) × RENB

(26)

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LM76005

SNVSBK5A – FEBRUARY 2020 – REVISED JULY 2020

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