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TMDS171 Datasheet(PDF) 24 Page - Texas Instruments |
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TMDS171 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 63 page  1 10 9 8 7 6 5 4 3 2 30 25 26 27 28 29 11 12 31 32 33 34 35 36 HPD_SRC GND OUT_D0p OUT_D0n TERM_CTL I2C_EN/PIN HPD_SNK IN_D1n IN_D1p IN_D2n IN_D2p IN_D0n IN_D0p IN_CLKn IN_CLKp OUT_D2p OUT_D2n OUT_D1p OUT_D1n OUT_CLKp OUT_CLKn SWAP/POL GND 1 10 9 8 7 6 5 4 3 2 30 25 26 27 28 29 11 12 31 32 33 34 35 36 TERM_CTL SWAP = Z In Normal Working SWAP = L In Swap Working CLOCK LANE DATA LANE0 DATA LANE1 DATA LANE2 OUT_D0p OUT_D0n HPD_SNK OUT_D2p OUT_D2n OUT_D1p OUT_D1n OUT_CLKp OUT_CLKn GND CLOCK LANE DATA LANE0 DATA LANE1 DATA LANE2 HPD_SRC GND I2C_EN/PIN IN_D1n IN_D1p IN_D2n IN_D2p IN_D0n IN_D0p IN_CLKn IN_CLKp SWAP/POL A1 A1 24 TMDS171, TMDS171I SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS171 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Figure 25. TMDS171 Swap Function 8.3.4 TMDS Inputs Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each input data channel contains an adaptive or fixed equalizer to compensate for Inter-Symbol Interference (ISI) due to cable, connector, and/or board trace losses. The voltage at the TMDS input pins must be limited under the absolute maximum ratings. TMDS input pins have incorporated failsafe circuits. An unused input channel can be externally biased to prevent output oscillation by connecting the N input pin to be grounded through a 1-k Ω resistor and the other pin left open. The input pins can be polarity changed through local I2C register when in retimer mode. 8.3.5 TMDS Inputs Debug Tools There are two methods for debugging a system to make sure the inputs to the TMDS171 are valid. A TMDS error checker is implemented to provide a rough Bit Error Rate per data lane. This allows the system implementer to determine how the link between the source and TMDS171 is performing on all three data lanes. See CSR BIT FIELD DEFINITIONS – RX PATTERN VERIFIER CONTROL/STATUS register. If a high error count is evident the TMDS171 has a way to view the general receiver eye quality. A tool is available that uses the I2C link to down load the data that can be plotted for an eye diagram. This is available per data lane. This tool also provides a method to turn on an internal PRBS generator that will transmit a data signal on the data pins. A clock at the proper frequency is required on the IN_CLK pins to generated the expected output data rate. 8.3.6 Receiver Equalizer The equalizer used to clean up inter-symbol interference (ISI) jitter/loss from the bandwidth-limited board traces or cables. TMDS171 supports fixed receiver equalizer and adaptive equalizer by setting the EQ_SEL/A0 pin or through I2C. When EQ_SEL/A0 is high, the EQ gain is fixed to 10 dB and when set low the EQ gain is set to 7.5 dB. TMDS171 operates in adaptive equalizer mode when EQ_SEL/A0 pin is left floating. The EQ gain will be automatically adjusted based on the data rate to compensate for trace or cable loss. Implementers can enable the various EQ settings through local I2C control. |
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