TMDS171 datasheet(32/63 Pages) TI2

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TMDS171, TMDS171I

SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017

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8.5.4 CSR BIT Field Definitions – Misc Control (offset: 00001001) (reset: 02h)

Figure 32. CSR Bit Field Definitions – Misc Control (09h)

R/W/U

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 8. CSR Bit Field Definitions – Misc Control (09h)

Bit

Field

Type

Reset

Description

Lane_SWAP

R/W/U

1’b0

This field Swaps the input lanes as per Figure 25.

0 --- Disable (default) No Lane Swap

1 --- enable: Swaps input lanes (Redriver and Retimer Mode)

Note: field is loaded from SWAP/POL pin; Writes are ignored

when I2C_EN/PIN = 0

LANE_POLARITY

R/W/U

1’b0

Swaps the input Data and Clock lanes polarity.

0 – Disabled: No polarity swap

1 – Swaps the input Data and Clock lane polarity (Retimer Mode

Only)

Note: field is loaded from SWAP/POL pin; Writes are ignored

when I2C_EN/PIN = 0

Reserved

1’b0

Reserved

SIG_EN

R/W/U

1’b0

This field enable the clock lane activity detect circuitry.

0 – Disable(Default) Clock detector circuit closed and receiver

always works in normal operation.

1 – Enable , Clock detector circuit will make receiver automatic

enter the standby state when no valid data detect.

Note: field is loaded from SIG_EN pin; Writes are ignored when

I2C_EN/PIN = 0

PD_EN

R/W

1’b0

0 – Normal working (default)

1 – Forced Power down by I2C, Lowest Power state

HPD_AUTO_PWRDWN_DISABLE

R/W

1’b0

0 – Automatically enters power down mode based on HPD_SNK

(default)

1 – Will not automatically enter power down mode

1:0

I2C_DR_CTL

R/W

2’b10

I2C data rate supported for configuring device.

00 – 5 Kbps

01 – 10 Kbps

10 – 100 Kbps(default)

11 – 400 Kbps (Note: HPD_AUTO_PWRDWN_DISABLE must

be set before enabling 400 Kbps mode)

TMDS171 Datasheet(PDF) 32 Page - Texas Instruments

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